(a) Field of the Invention
The present invention relates to a metal-semiconductor junction field effect transistor (MESFET) and, more particularly, to a structure of electrodes of a MESFET.
(b) Description of the Related Art
Various methods have been used in fabrication of a MESFET to form electrodes and interconnects thereof. A method for manufacturing a conventional GaAs MESFET will be described first with reference to FIGS. 1A to 1K.
A GaAs substrate designated by reference numeral 100 includes a substrate body 101 made of undoped GaAs (i-GaAs) and an n.sup.+ -GaAs layer 102 doped with Si at a concentration of 2.times.10.sup.18 atoms/cm.sup.3 and formed on the substrate body 101 to a thickness of 60 nanometers (nm).
First, a SiO.sub.2 film 2 is formed on the GaAs substrate 100 to a thickness of 300 nm (FIG. 1A). A photoresist pattern 26 is then formed on the SiO.sub.2 film 2, and a gate electrode opening 27 is formed in the SiO.sub.2 film 2 by reactive ion etching with CF.sub.4 gas and using the photoresist pattern 26 as a mask (FIG. 1B). After removal of the photoresist pattern 26, a surface portion of the n.sup.+ -GaAs layer 102 of the GaAs substrate 100 exposed in the gate electrode opening 27 is removed by a wet etching using a phosphoric-acid-based etchant, whereby a gate recess 28 is formed on the n.sup.+ -GaAs layer 102 beneath the gate electrode opening 27 (FIG. 1C). The recess 28 is formed in order to adjust the threshold voltage of the finished MESFET.
Subsequently, a WSi.sub.x metallic film 29 having a high melting point and a relatively high resistivity is deposited by sputtering in a thickness of 500 nm (FIG. 1D), and subjected to patterning together with the SiO.sub.2 film 2 to form a gate electrode 29A by reactive ion ethching with CF.sub.4 and SF.sub.6 gas mixture and using a second photoresist film 31 as a mask, gate electrode 29A having a Schottky contact 30 between the same and the n.sup.+ -GaAs layer 102 (FIG. 1E). After removal of the second photoresist pattern 31, a third photoresist pattern 42 is formed to cover the gate electrode 29A, the photoresist pattern 31 having openings 43 for exposing the n.sup.+ -GaAs layer 102 at the locations where source and drain electrodes are to be formed. A metallic laminate 44 including AuGe/Ni/Au films is then deposited on the entire surface including the surface of the n.sup.+ -GaAs layer 102 at the bottom of the openings 43 (FIG. 1F). The metallic laminate 44 formed on the photoresist pattern 42 is then removed by a lift-off method. A heat treatment is then performed to form alloy ohmic contacts 44A between the source and drain electrodes to be formed and the n.sup.+ -GaAs layer 102 (FIG. 1G).
Thereafter, a second SiO.sub.2 film 32 is deposited (FIG. 1H) on the entire surface and subjected to planarization (FIG. 1I). Subsequently, a gate electrode contact hole 34, a source electrode contact hole 35, and a drain electrode contact hole 36 are formed in the SiO.sub.2 film 32 by a photolithographic technique using a fourth photoresist pattern 33 as a mask (FIG. 1J).
After removal of the photoresist pattern 33, a metallic laminate 37 including Ti/Pt/Au films and having a small resistance is deposited on the entire surface including the surfaces of SiO.sub.2 film 32, gate electrode 29A and the alloy ohmic contacts 44A for the source and drain (FIG. 1K). The metallic laminate 37 is then subjected to patterning by Arion milling and using a fifth photoresist pattern 38 as a mask, thereby obtaining source electrode 40, gate interconnect 39 and drain electrode 41 (FIG. 1L). Finally, as a result of removal of the fifth photoresist pattern 38, a finished MESFET is obtained (FIG. 1K). The Ti/Pt/Au metallic laminate 39, 40, 41 has a small resistance to thereby obtain a high speed operation of the resultant MESFET.
With the process for manufacturing the conventional MESFET as described above, a large number of deposition and photolithographic steps are needed, which increases fabrication costs of the MESFET.